1. Field of the Invention
The present invention relates to a semiconductor memory using complementary metal-oxide-semiconductor transistors and a storage capacitor, and more particularly to a structure and fabrication process for a random-access-memory cell for dynamic operation for large scale integrated circuit technology.
2. Description of the Prior Art
U.S. Pat. No. 4,633,438 issued Dec. 30, 1986 to Kume et al, entitled "STACKED SEMICONDUCTOR MEMORY", describes a 3-transistor random access memory for dynamic operation, in which one of the transistors is stacked on the other transistor. A transistor for writing is disposed on a transistor for reading, and one of its terminals is used in common with the gate electrode of a transistor for judging data. The other terminal is connected to one of the terminals of the transistor for reading.
A memory cell capable of extremely large scale integration can be obtained using stacked complementary FETs, wherein the two FETs are driven by overlapping wordlines; however, the wordlines are separately driven for read and write operations, rather than simultaneously driven with complementary signals as in the present invention.
U.S. Pat. NO. 4,271,488 issued Jan. 2, 1981 to Saxe entitled "HIGH-SPEED ACQUISITION SYSTEM EMPLOYING AN ANALOG MEMORY MATRIX", describes a high-speed acquisition system employing a analog memory matrix in which sample-hold elements connected to an analog bus are arranged in rows and columns to form an M x N matrix. The system is operable in a fast in - slow out mode, and the analog memory matrix may be implemented on a single integrated-circuit semiconductor chip. The analog memory comprises cells containing sample/hold circuits. Typical sample/hold circuits are shown in FIG. 2, including FIG. 2C which shows a complementary FET switching means. However, the complementary drive signals are obtained within the cell by means of inverter 54 and AND gate 52, and this patent does not show or teach the use of complementary wordlines for providing the complementary drive signals as set forth in the present invention.
U.S. Pat. No. 3,701,120 issued Oct. 24, 1972 to Charters et al, entitled "ANALOG CAPACITOR MEMORY WITH SLOW WRITE-IN AND FAST NONDESTRUCTIVE READ-OUT" describes an analog memory capable of write-in at a relatively low rate and independent, nondestructive read-out at a relatively high rate. A single write-in add read-out address logic is provided for as memory units are desire. Each memory unit includes a matrix of sample and hold microcircuits, each having an external storage capacitor, an isolation amplifier and independent input and output analog switching in response to vertical and horizontal write-in and read-out addressing.
U.S. Pat. No. 3,457,435 issued July 22, 1969 to Burns et al, entitled "COMPLEMENTARY FIELD-EFFECT TRANSISTOR TRANSMISSION GATE", describes a circuit wherein a pair of field-effect transistors of opposite conductivity type have their source-drain paths connected in parallel. Signals of opposite polarity sense are applied at the gates of the transistors to bias both on or both off simultaneously. The gate comprising complementary FETs is driven by two complementary signals as shown in FIG. 4, in order to eliminate the drop in transmitted voltage due to the threshold voltage of a single FET. This patent does not disclose usage within a DRAM cell.
Pat. EP 175-378A of Fujitsu LTD shows three-transistor cell DRAM structure which has read and write select lines combined into one line connected to gates of both read and write select transistors. A write selector transistor is disposed over a read select transistor, the two being separated by an insulator layer and sharing a drain region. A storage transistor is formed on a silicon substrate in the same level as the read select transistor. Channel regions of the two transistors are connected to one another and each is used as a diffusion (source or drain) region of the other two transistors.
Write and read select lines may be combined into a single control line or a write/read select line. Here gate electrodes of the read and write select transistors are connected t the write/read select line and are distinguished by having different threshold voltages.
Other reference include U.S. Pat. Nos. 4,434,433; 4,308,595; 4,203,159; 4,044,342; 3,919,569 and IBM Technical Disclosure Bulletins Vol. 23, No. 10 Mar, 1981, Page 462 and Vol. 18, No. 3, Page 649 Aug, 1975.